Semiconductor memory device and arrangement method thereof
US7295454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2005 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Oct 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.