Phase alignment circuitry and methods
US7295641B1 · kind B1 · utility
7Cited by
13References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling clock signal (derived from the reference clock signal). Information about which amounts of progressively greater phase shift in the sampling clock signal cause loss of alignment between a training pattern and training data in the data signal can be used for such purposes as identifying the amount of phase of shift of the reference clock signal that will be best for use in sampling the data signal during normal (post-training) operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.