Circuit and method to provide configuration of serial ATA queue depth versus number of devices
US7296094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2004 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Oct 3, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an expanded ability to support additional SATA end devices by configuring the allowed native command queue depth to be smaller for each SATA end device, thus allowing more SATA end devices to be supported by a single SAS host controller. An embodiment of the invention has three possible preset configuration states: thirty-two SATA end devices with a native command queue depth of thirty-two; sixty-four SATA end devices with a native command queue depth of sixteen; and one-hundred-twenty-eight SATA end devices with a native command queue depth of eight.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.