Buffer bypass circuit for reducing latency in information transfers to a bus
US7296109B1 · kind B1 · utility
4Cited by
20References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit comprises a multiplexer and logic configured such that the information to be transferred is either buffered in a buffer if a grant generated by the bus arbiter indicates that the bus is unavailable, or transferred directly to the bus if the grant indicates that the bus is available and the buffer is empty at the time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.