Mechanism that provides efficient multi-word load atomicity
US7296120B2 · kind B2 · utility
37Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2004 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Dec 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.