Memory interface supporting multi-stream operation
US7296124B1 · kind B1 · utility
23Cited by
4References
20Claims
0Family size
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Inventor
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Aug 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data occurs within sequential transactions. Each transaction is associated with a block of consecutive memory locations and with a starting address. The interface controller includes at least two address buffers, each for storing any of the starting addresses and any address obtained by incrementation thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.