System, method and storage medium for providing a serialized memory interface with a bus repeater
US7296129B2 · kind B2 · utility
46Cited by
107References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2004 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.