Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle
US7296176B1 · kind B1 · utility
0Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2005 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | May 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. The system then uses the clock signal to limit the maximum repetition rate of the asynchronous circuit so that only a predetermined number of asynchronous transactions may take place during each cycle of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.