Method and system for generating parallel decodable low density parity check (LDPC) codes
US7296208B2 · kind B2 · utility
23Cited by
0References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2004 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.