Patent · US Active

Multiple match detection circuit and method

US7298637B2 · kind B2 · utility

5Cited by

15References

20Claims

0Family size

Assignee

Mosaid Technologies Incorporated · CA

Inventors

Stanley Jeh-Chun Ma · Ottawa, CA
Peter Ma · Shanghai, CN

Key dates

Filing date	Jul 24, 2006
Grant date	Nov 20, 2007
Priority date	—
Expiry date	Jul 24, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG11C15/046
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.