Architecture for virtual ground memory arrays
US7298651B2 · kind B2 · utility
4Cited by
6References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The drain programming window in virtual ground memory arrays may be enlarged by reducing the number of voltage drops in the cell access path. This reduction may be accomplished by reducing the number of transistors in the access path or by otherwise reducing the resistance in the access path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.