Ferroelectric random access memory
US7298657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2006 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jun 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.