Method and system for accelerated detection of weak bits in an SRAM memory device
US7298659B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Nov 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical “0” and logical “1”. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.