Low frequency self-calibration of a PLL with multiphase clocks
US7298790B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop is coupled to the Phase Frequency Detector, and comprises a Calibration Charge Pump, a Demultiplexer and Y Calibration Loop Filters, with Y being an integer. The Control Logic controls the Phase-Switching Fractional Divider and the Demultiplexer. A Reference Frequency Signal is coupled to the Phase Frequency Detector and a Calibration Signal is coupled to the calibration loop. The main loop further comprises a Phase-adjusting Block coupled to a Multiplexer. The Phase-adjusting Block is arranged so as to receive at least one correction signal from the calibration loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.