Multiple date rate filtered modulation system for digital data
US7298791B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2003 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Mar 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2017
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In an exemplary embodiment, a multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. A direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. A multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. A multi-rate digital data filter receives the converted digital data and produces a filtered digital output. An output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, an adder combines the scaled and filtered digital output with a center frequency input and produces the converted output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.