Multi-modulus programmable frequency divider
US7298810B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2004 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Sep 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable frequency divider for dividing the frequency of a source signal according to a selectable divisor which is obtained based on a plurality of divisor signals and outputting a result signal having a divided frequency includes at least one cell of a first type. The cells of the first type are cascaded with each other. The programmable frequency divider synchronously resets all of the cells of the first type according to a reset signal in order to selectively switch each cell of the first type to perform a divide-by-two or divide-by-three operation according to a corresponding divisor signal. The last cell of the first type outputs the result signal having the divided frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.