Scaling address space utilization in a multi-threaded, multi-processor computer
US7299336B2 · kind B2 · utility
1Cited by
2References
21Claims
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Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Oct 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Scaling address space utilization in a multi-threaded, multi-processor computer, including attaching to process memory of an exporting process a region of virtual memory specified in a cross-memory descriptor; requesting, by an importing thread of an importing process having process memory, a lightweight attachment of the region of virtual memory to the process memory of the importing process for exclusive use by the importing thread; and lightweight attaching, by an operating system to the process memory of the importing process, the region of virtual memory for exclusive use by the importing thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.