Patent · US Expired

Test circuit, integrated circuit, and test method

US7299389B2 · kind B2 · utility

11Cited by
3References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 29, 2004
Grant dateNov 20, 2007
Priority date—
Expiry dateJan 22, 2026

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318572
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A test circuit comprises a selector SEL1 having a first input to which signals M1OUT from a macro block MB1 are input and a second input to which test input signals TIN1 and TIN2 for a macro block MB2 are input, and a selector SEL2 having a first input to which a signal SQ from the SEL1 is input and a second input to which a signal M2OUT from the MB2 is input. In a first test mode in which the MB1 is tested, the SEL1 outputs the signals M1OUT from the MB1 to a first input of the SEL2, and the SEL2 outputs the signal SQ from the SEL1 to the MB1. In a second test mode in which the MB2 is tested, the SEL1 outputs the test input signals TIN1 and TIN2 for the MB2 to the MB2, and the SEL2 outputs the signals M2OUT from the MB2 as a test output signal TOUT for the MB2.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.