Decoding apparatus, decoding method, and program to decode low density parity check codes
US7299397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2004 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jul 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6577
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.