Method and apparatus for parallelly processing data and error correction code in memory
US7299399B2 · kind B2 · utility
16Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 11, 2004 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcting the first data according to the first syndrome, while reading the second data, and calculating the second syndrome based on the second data and the second ECC code, (3) and correcting the second data according to the second syndrome, while reading the third data and calculating the third syndrome based on the third data and the third ECC code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.