Method for improving efficiency in laying out electronic components
US7299441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jan 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is proposed for improving the layout efficiency in laying out electronic components, which is applicable to information processing equipment, to accelerate the layout of electronic components. First, a first two-dimensional plan view including various electronic component members is preset using a drafting software platform. Subsequently, the two-dimensional plan view is converted to a text file and all the relevant data of the electronic components contained in the two-dimensional plan view are encoded in the text file. Then, all of the electronic component members contained in the first two-dimensional plan view are displayed in a second two-dimensional plan view, and a function selection menu is generated by an arithmetic process. Therewith, a user is able to select the data of the electronic component contained in the text file via the function selection menu to perform the layout operations for a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.