Enabling efficient design reuse in platform ASICs
US7299446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | May 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and a custom chip specification. The generation module may be configured to generate Register Transfer Level (RTL) views for the semiconductor chip. The first synthesis module may be configured to perform logic synthesis using the RTL views. The user interface module may be configured to query a user whether re-usable intellectual property (IP) is to be generated. The extraction module may be configured to extract and package design information for the re-usable IP in response to a request from the user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.