Circuit layout for improved performance while preserving or improving density
US7301182B1 · kind B1 · utility
3Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | May 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
Abstract
In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be electrically isolated from an input to the bent-gate input stage transistor by forming at least one bent-gate grounded-gate transistor between the bent-gate output stage transistor and the input to the bent-gate input stage transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.