Duplicated double checking production rule set for fault-tolerant electronics
US7301362B2 · kind B2 · utility
13Cited by
1References
14Claims
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Key dates
| Filing date | Mar 14, 2006 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | May 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.