High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
US7301370B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2004 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | May 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.