Time-interleaved analog-to-digital converter having timing calibration
US7301486B2 · kind B2 · utility
15Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2006 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Jul 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) having a two-channel or multi-channel structure processes background timing calibration. Signals from the ADC are directly compared for the calibration. Additional signal or interruption of circuit is not required. A dynamic calibration is processed. A timing-skew error is kept in a low level and a process mismatch is not a concern. Moreover, sampling frequency and input signal frequency are improved. A high sampling frequency and a high speed of signal inputting are achieved; and chip area can be greatly shrunk because the extra calibration circuits are simple digital circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.