Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
US7301832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | May 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the content addressable memory. During a memory access cycle a register in the content addressable memory latches a memory address. The content addressable memory decodes the address and produces column redundancy information as an output. The column redundancy information is latched during a period complementary to the memory access cycle. By utilizing complementary memory access phases to latch memory addresses in contrast with a utilization of column redundancy information, a single set of registers may be used. Additionally, concurrent read and write operations are supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.