Cycle-efficient TDM timeslot remapping for network processing engines
US7301958B2 · kind B2 · utility
8Cited by
5References
31Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Feb 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for remapping channel data are presented. Multiple successive frames carrying data in timeslots are received. The timeslots are assigned to channels so that data for the channels includes interleaved data. The data from the multiple successive frames for each of a predetermined number of the timeslots are aggregated. The aggregated data is mapped, by timeslot, to produce a timeslot-based map. The aggregated data of the timeslot-based map is remapped to produce a channel-based map in which the data for the channels are grouped together by channel in the order that the data were received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.