Method and apparatus for improved high-speed adaptive equalization
US7301997B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2001 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Dec 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/6971
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.