Phase estimator with bias correction
US7302016B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and serial detector for demodulating a phase-modulated signal are presented. In particular, a carrier phase estimator applies a phase estimate to an output of a matched serial filter. The filter output is matched to the first Laurent pulse of the received signal, and the phase estimate corrects for a phase bias introduced by using the first Laurent pulse. The method and detector are particularly valuable in Gaussian Minimum Shift Keying (GMSK) modulated systems and where then product of the bandwidth B and the bit rate Tb is less than about 0.3, and where a training sequence in a header of a burst system has a length L0 less than about 5000. Three estimates of phase offset are given, each taking the inner product of x and the conjugate transpose of either a or p; wherein x is a vector of data samples, a is a vector of pseudo symbols, and p is a vector of the data and ISI portions of the samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.