Apparatus and method for high speed data transfer
US7302508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Feb 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved target and initiator. The initiator provides a starting address and length information on a bus synchronously with a clock signal. While the starting address and length information are present on the bus, the initiator provides a write or a read request signal that is activated and deactivated synchronously. The initiator then receives from the target unit a grant signal that is activated and deactivated synchronously. After the grant signal is deactivated, for a write operation, the initiator provides a number of write data items on the bus synchronously for capture by the target unit. For a read operation, the target provides a number of read data items on the bus synchronously for capture by the initiator unit. One data item provided in each clock cycle of the clock signal and the number of data items is determined by the length information provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.