Caching bypass
US7302528B2 · kind B2 · utility
5Cited by
1References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Nov 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30047
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, in one aspect, the disclosure describes a method that includes providing a memory access instruction of a processing element's instruction set including multiple parameters. The parameters include at least one address and a token specifying whether the instruction should cause data retrieved from memory in response to the memory access instruction to be unavailable to a subsequent memory access instruction via a cache
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.