System for processing VLIW words containing variable length instructions having embedded instruction length identifiers
US7302552B2 · kind B2 · utility
16Cited by
6References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 14, 2004 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | May 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.