Method for verifying a circuit design by assigning numerical values to inputs of the circuit design
US7302655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Mar 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying a circuit design includes a step of assigning numerical values 1/ai to input ports of the circuit design according to a function ai+1=(ai−1)2+1, wherein i represents the number of the input port and the numerical value a1 is not equal to 2 or 1. Preferably, a1 is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l's probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.