Method and system for hermetically sealing packages for optics
US7303645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2003 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/1093
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for hermetically sealing devices. The method includes providing a substrate which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The method also provides a transparent member of a predetermined thickness which includes a plurality of recessed regions arranged in a spatial manner as a second array and a standoff region. The method also includes aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. The method further includes hermetically sealing each of the chips within one of the respective recessed regions by using at least a bonding process to isolate each of the chips within one of the recessed regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.