Area efficient programmable frequency divider
US7304513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Apr 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.