Delay circuit and semiconductor device including same
US7304520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2006 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Jan 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when a delay operation is enabled based on a corresponding control signal. However, where the delay operation of a delay block is disabled based on the corresponding control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.