Automatic phase lock loop design using geometric programming
US7304544B2 · kind B2 · utility
7Cited by
21References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Feb 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.