Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
US7304875B1 · kind B1 · utility
31Cited by
106References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 19, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Apr 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in self repair (BISR) of hard memory defects and/or compare logic defects in the plurality of CAM array blocks concurrently with operations to search entries in the plurality of CAM array blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.