DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers
US7305499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.