Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
US7305500B2 · kind B2 · utility
25Cited by
197References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Oct 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.