Multiple master buses and slave buses transmitting simultaneously
US7305510B2 · kind B2 · utility
59Cited by
11References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Aug 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.