Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories
US7305521B2 · kind B2 · utility
5Cited by
7References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic Frequency Scaling (DFS) cache memories that can be accessed during an idle time in a single low frequency DFS clock cycle are disclosed. The access can begin during the idle time in the single low frequency DFS clock cycle and may continue during a subsequent low frequency DFS clock cycle. The idle time can be a time interval in the single low frequency DFS clock cycle between completion of a single high frequency DFS clock cycle and completion of the single low frequency DFS clock cycle. Related circuits and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.