Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations
US7305543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Jul 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address. This target pointer address is then used as an address to access RAM without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.