Patent · US Expired

Method and system for formal unidirectional bus verification using synthesizing constrained drivers

US7305636B2 · kind B2 · utility

1Cited by

0References

24Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Jason R. Baumgartner · Austin, US
Tilman Gloekler · Schrobenhausen, DE
Joachim Kneisel · Stuttgart, DE
Johannes Koesters · Holzgerlingen, DE

Key dates

Filing date	Feb 24, 2005
Grant date	Dec 4, 2007
Priority date	—
Expiry date	Jan 15, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3323
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.