Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip
US7305639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Feb 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.