Compound semiconductor wafer and manufacturing method thereof
US7307290B2 · kind B2 · utility
7Cited by
4References
13Claims
0Family size
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Key dates
| Filing date | Apr 13, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Apr 13, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
Abstract
A compound semiconductor wafer providing an InGaAs light receiving layer having superior crystal characteristic suitable for a near-infrared sensor includes an InAsxP1-x graded buffer layer consisting of a plurality of layers positioned on an InP substrate and an InAsyP1-y buffer layer positioned on the graded buffer layer, sandwiched between said InP substrate and the InGaAs layer, wherein maximum value of PL light emission intensity at an interface of each of the layers of the graded buffer layer and the buffer layer is, at every interface, smaller than 3/10 of the maximum PL light emission intensity of the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.