Memory with five-transistor bit cells and associated control circuit
US7307873B2 · kind B2 · utility
3Cited by
8References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2006 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.