Natural analog or multilevel transistor DRAM-cell
US7307877B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Nov 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.