Computer system and network interface supporting dynamically optimized receive buffer queues
US7307998B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jul 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9052
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network interface comprises the first port on which incoming data is transmitted and received at the data transfer rate of the network, a buffer memory coupled to the first port, and a second port coupled with the buffer memory, and through which transfer of packets between the host system, and the buffer memory is executed. A driver in the host system allocates a plurality of sets of receive buffers, where each set of receive buffers is composed of receive buffers having different sizes. A receive buffer descriptor cache located at the interface level stores receive buffer descriptors corresponding to receive buffers in the plurality of sets. As incoming packets arrive at the interface, logic determines the size of the incoming packet and assigns the packet to a receive buffer descriptor in the receive buffer descriptor cache according to the determined size. Upload logic at the interface level manages the uploading of packets from the buffer memory to the host system using the assigned receive buffer descriptors. A driver in the host dynamically adjusts the sizes of receive buffers in response to statistics about packet size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.